Power consumption in integrated circuits has become increasingly important primarily due to wide spread use of battery powered portable and handheld appliances. As integrated circuits develop, lower power implementations of digital and analog circuits are constantly being developed. CMOS (complementary metal oxide silicon) compared to the earlier developed TTL (transistor transistor logic) provides a simple example. Some of the characteristics of TTL logic circuits include power dissipation that is usually 10 mW per gate, voltage levels that range from 0 to Vcc where Vcc is typically 4.75V to 5.25V. For TTL, a voltage range of 0V-0.8V creates a logic level 0 or low while a voltage range of 2V-Vcc creates a logic level 1 or high. Whereas, some of the characteristics of CMOS logic circuits include much lower power dissipation, typically 10 nW per gate, since there is complementary-symmetry. The complementary-symmetry refers to the typical design style with CMOS using complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions. Since one transistor of the pair is always off, CMOS devices provide low static power consumption. The series combination of CMOS devices only draws significant power momentarily during switching between on and off states. Another important characteristic of CMOS devices is high noise immunity, a logic level 0 or low is between 0 and ⅓ VDD while a logic level 1 or high is between ⅔ VDD and VDD. With high noise immunity, lower supply power can be used. Although, power consumption can be reduced by lowering the supply voltage, lowering the supply voltage does not work for all circuits. In IC design, hybrid circuits requiring different input voltages are not uncommon, and circuits using lower voltage power supplies are frequently connected with circuits using higher voltage power supplies.
Particularly in multi-core system-on-chip (SoC) integrated circuits that are often used to process multimedia data in appliances and consumer devices such as cellular phones, high-speed operation and low-power consumption are much desired features. Conventionally, high speed performance is achieved by transistor scaling and low-power operation by supply-voltage scaling. However, circuits that include SRAM bitcells require more power and limit power supply scaling in SoC's. Dual-rail or dual-supply memory designs are needed to enable SoC voltage scaling to achieve optimum power consumption, speed, durability while still being able supply a higher voltage level for the SRAM bitcell. Another challenge with the dual-rail or dual-supply memory designs is pulse-width for the generated clock signal to access the SRAM bitcells. Often times, the pulse-width for the generated clock to access the SRAM bitcell is similar to the main clock. However, in order to avail integrated circuit designers extra flexibility, increased margins, robustness to their circuit designs, it is preferable to generate a level-shifted internal clock that is independent of the external clock pulse-width. Also, these dual-rail or dual-supply memory designs having level-shifter circuits introduce additional delay to the clock path for the SRAM bitcell. The overall result is loss of flexibility, reduced margins, lack of robustness to circuit designs in addition to slower access time, response, and additional delay associated with access to the SRAM bitcell. Accordingly, there is a need for a level-shifter that minimizes delay of voltage level-shifting from an external clock on a first logic supply voltage to an internal clock on a higher array supply voltage that is pulse-width independent of the internal clock used to generate the internal clock on the higher array supply voltage.